High-bandwidth memory (HBM)

Why the concentration exists

High-bandwidth memory stacks DRAM dies vertically using through-silicon vias, creating a memory-dense chip co-packaged with GPUs and ASICs on silicon interposers. HBM achieves roughly three times the throughput of GDDR5 while consuming only 20% of the power, because shorter signal traces on the silicon interposer reduce energy per bit transferred. The 3D stacking and low-voltage operation deliver higher bandwidth than DDR4 or GDDR5 in a substantially smaller form factor, which is why AI accelerators depend on it for the memory bandwidth required by large model training.[1][2][9][24]

Manufacturing HBM requires advanced packaging technologies that concentrate supply among established players. SK hynix uses mass reflow-molded underfill technology, which offers roughly twice the thermal conductivity compared to alternative NCF approaches. The company's HBM3E introduces all-around power TSVs on the die, increasing the number of TSVs by almost six times and achieving up to 75% lower IR drop for VPP. These packaging innovations create barriers to entry beyond the already substantial DRAM fabrication requirements.[10][12][15]

What the evidence shows

Who supplies it

Advanced packaging capacity constraints limit HBM supply growth despite strong demand. SK hynix has told investors that its advanced packaging lines are at capacity through 2026, and Micron faces similar constraints with its advanced packaging lines. SK hynix's HBM production for 2026 was already sold out due to firm customer commitments. These bottlenecks persist even as manufacturers expand fabrication capacity.[11][16]

What it depends on, and what depends on it

HBM sits between DRAM fabrication and AI accelerator assembly, transforming commodity DRAM dies into specialized memory stacks for high-performance computing. Most AI processors use HBM as it provides the highest memory bandwidth available today, including compute GPUs from AMD and NVIDIA, specialized processors like Intel's Gaudi, and AWS's Inferentia and Trainium. The memory is placed directly on the GPU die, which means GPUs will not have different capacities, though portions can be disabled.[3][6]

Each HBM generation increases bandwidth and capacity through more channels, higher data rates, and greater stack heights. HBM3 delivers approximately 819 GB/s per stack via a 1024-bit interface at roughly 6.4 Gbps, with SK hynix's HBM3 chips capable of 6.4 Gbps per pin reaching up to 819 GB/s under peak conditions. The NVIDIA H100 achieves around 3 TB/s with five HBM3 stacks. HBM4 doubles the interface to 2048 bits, uses 32 channels, and supports data rates reaching 8 Gb/s per pin for 2 TB/s per stack with capacities up to 64 GB.[8][23][24][20]

HBM4E pushes bandwidth even further, with specifications supporting data rates up to 16 Gb/s and reaching up to 3.6 TB/s per stack. SK hynix completed development and prepared mass production of HBM4 as of September 2025, implementing over 10 Gbps operating speed that exceeds the JEDEC standard of 8 Gbps. HBM4 doubles bandwidth through adoption of 2048 I/O terminals and improves power efficiency by more than 40% compared to the previous generation.[5][9][18]

Where it sits in the stack

What would break it

Samsung and Micron are expanding HBM capacity to challenge SK hynix's market leadership. Samsung plans to expand its HBM production capacity by around 50% in 2026. Samsung shipped HBM4 samples with 11 Gbps pin speeds in late 2025, matching Micron's performance records, and plans mass production by the end of that year. Micron announced commercial production of its HBM3E in February 2024 for NVIDIA's H200 Tensor Core GPUs shipping in Q2 2024.[7][13][14]

SK hynix is investing heavily to maintain its lead through vertical integration and new facilities. The company is investing 19 trillion won, approximately $13 billion, in a new HBM packaging facility called P&T7 in Cheongju, South Korea, due to be completed by the end of 2027. SK hynix's P&T7 plant will be operationally linked with Fab M15X, creating a vertically integrated manufacturing ecosystem for HBM dies that are three to four times larger than commodity DDR5.[11][10]

Alternative memory architectures could eventually reduce dependence on HBM, though timelines remain distant. SanDisk and SK hynix are sponsoring a standardization effort at OCP for High Bandwidth Flash, with sample availability anticipated in the second half of 2025 and systems appearing in 2027. HBF offers capacity of 256 GB per die, giving 512 GB per 16-high stack with read bandwidth of 1.6 TB/s. Over the next five years, HBM will increasingly merge with chiplet architectures, with HBM4 expected around 2026-2027 delivering bandwidth beyond 2 TB/s through active interposers.[17][4]

What to watch

Samsung will begin shipping HBM4 chips to NVIDIA in February 2026, marking a significant capacity expansion for the Korean manufacturer. Micron's full 2026 HBM4 production capacity is already sold out. SK hynix signed an agreement with TSMC in April to develop and produce next-generation HBM, with production starting in 2026. These developments signal continued tight supply through the HBM4 generation.[22][13]

SK hynix's P&T7 advanced packaging facility in Cheongju is due for completion by the end of 2027, adding substantial capacity for HBM die production. The company began mass production of the world's first 12-layer HBM3E with 36 GB capacity on September 26, 2024, achieving memory speed of 9.6 Gbps. SK hynix will begin full-scale mass production of LPDDR6 in the second half of 2026, serving mobile customers like Xiaomi.[11][19][21]

Related nodes

Sources

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