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CXL memory and memory expanders

BOTTLENECK

CXL controller ASIC IP margin is captured by Astera Labs, bottlenecking memory pool deployment despite commoditized DRAM.

Memory pools attached over CXL protocol, expanding beyond CPU socket limits. Enables larger inference KV-cache and model-weight staging for multi-GPU serving. CXL controller ASIC vendors Astera Labs and Montage Technology capture IP margin; DRAM suppliers commoditised.

Why the concentration exists

Compute Express Link is a memory interconnect protocol that expands server memory capacity beyond the limits of direct-attached DDR channels. CXL memory controllers typically add about 200 nanoseconds of latency to memory access, which creates a tiered-memory architecture where CXL-attached DRAM is slower than local DDR5. CXL DRAM presents two to three times longer access latency than DDR DRAM, so workloads must be optimized to place frequently-accessed data in local memory while using CXL for larger capacity pools.[5][10]

The protocol has evolved through multiple specification revisions that each add capabilities and complexity. CXL 1.0 was released in 2019 with basic coherency and memory protocols, while CXL 2.0 introduced memory pooling, switching, and persistent memory support in 2020 and 2021. CXL 3.0 added enhanced coherency semantics and support for memory sharing between multiple devices, and CXL 3.1 uses the PCIe 6.1 physical layer to scale data transfers to 64 GT/s supporting up to 128 GB/s bi-directional communication over a x16 link.[8][10][13][15]

CXL 2.0 supports switching to enable memory pooling, allowing up to 16 hosts to simultaneously access different portions of memory from a single device partitioned as multiple logical devices. CXL 3.0 fabric supports up to 4,096 nodes with port-based routing for memory sharing and disaggregation. The specification evolution creates qualification challenges because the spec advances faster than OEM platforms can implement each version.[3][13][14]

What the evidence shows

Almost none of the CXL memory modules are buyable on the open market in 2026 in any volume resembling 'stock'.

cosolvic.com
RESCORED JUL 2026fragmentedscaling15 companies

Who supplies it

Merchant CXL controllers are supplied by a separate set of semiconductor vendors that capture the IP margin for the protocol logic. Lead suppliers for standalone CXL controller ICs include Astera Labs Leo, Montage Technology MXC, Microchip SMC2000, and Marvell Structera A. Montage Technology's M88MX6852 controller supports DDR5-8000 and is widely used in disaggregated AI memory architectures in 2026.[16][20][21]

CXL switches and fabric components represent a third supplier category with different market participants. Lead suppliers for CXL switches and fabrics include Marvell Structera S, XConn Technologies XC50256, Panmnesia, and Enfabrica. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach larger memory pools without extending latency.[4][20]

Who controls it

MicronSamsungSK Hynix+12 more tracked
$2.0B market · 2025source

What it depends on, and what depends on it

CXL memory modules are built from commodity DRAM dies combined with a specialized CXL controller ASIC. Micron's CZ120 modules use Micron's 1α DRAM production node and a PCIe 5.0 x8 interface to deliver up to 36 GB/s of bandwidth. The modules come in the E3.S 2T form factor with capacities of 128GB and 256GB, and adding four 256GB CZ120 modules to a server can enable 24 percent greater memory read/write bandwidth per CPU.[6][7][12]

CXL add-in cards can provide substantially larger memory capacities than direct-attached DIMM configurations. SMART Modular's CXL-enabled AICs can add up to 4TB of memory and are available in 8-DIMM and 4-DIMM configurations, with the 8-DIMM version providing 64GB/s bandwidth via two CXL controllers. Penguin Solutions' MemoryAI KV Cache Server is a 4U rackmount CXL-based memory server that provides up to 11TB of total memory including 8TB of DDR5 CXL memory.[6][17]

CXL memory expansion serves AI inference workloads that require large memory pools for KV-cache and model-weight staging. SK Hynix introduced its Inference Memory Tiering Expansion architecture, which improves AI inference efficiency by 35.7 percent over conventional systems by placing CXL hybrid memory between HBM/DDR and SSD. Samsung's CMM-D has delivered up to 19 percent performance improvements in VectorDB and RAG systems compared to DRAM-only configurations.[9][16]

Where it sits in the stack

Takes in: DDR5 DRAM dies, CXL controller ASIC, PCIe Gen5 interface

Sends on: Expanded memory pool accessible over CXL fabric from host CPU

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What would break it

CXL memory modules face a significant availability gap between announced products and purchasable inventory. The parts are real, the silicon is real, and the OEM data sheets are real, but almost none of it is buyable on the open market in 2026 in any volume that resembles stock. System architects requesting quotes for specific modules like the Micron CZ120 256GB face uncomfortable answers about actual availability.[1]

Specification advancement creates implementation gaps that affect supply chain readiness for each new CXL generation. Between the time the spec was released and the introduction of initial OEM platforms supporting the 1.1 standard, the spec had advanced much further. CXL 4.0 specification is projected to double bandwidth to 128GT/s, continuing the pattern where specifications move faster than volume production can follow.[2][3]

What to watch

Samsung Electronics targets mass production of CXL 3.1 memory in the fourth quarter of 2026, with plans to ship next-generation CXL 3.1 memory samples in the second half of 2026. Samsung's CMM-D 3.1 module supports memory capacity of up to 1 terabyte and bandwidth of 72 gigabytes per second based on the PCIe 6.0 interface. Samsung also plans to mass-produce its CXL Memory Module-DRAM 3.0 based on the CXL 3.2 specification by the end of 2026.[9][18][19]

SK Hynix showcased samples of its second-generation CMM-DDR5 featuring CXL 3.2 at the HPED 2026 exhibition and has entered supply discussions with customers. The CXL 3.2 specification introduces the CXL Hotpage Monitoring Unit feature to optimize data movement across memory devices. SK Hynix aims for mass production of CXL 2.0 type 3 memory devices within 2024.[9][11][19]

Microsoft launched its first CXL-equipped cloud instances in November 2025. Montage Technology introduced a CXL 3.1 Memory eXpander Controller on August 27, 2025. More than 90 percent of newly shipped servers are CXL-capable in 2026, creating a large installed base for memory expansion adoption.[2][16][21]

Related nodes

High-bandwidth memory (HBM)Server DRAM (DDR5 and LPDDR5)Non-volatile memory and emerging NVM (PCM, RRAM)

Sources

  1. cosolvic.com · 2026-06-11T09:00:00
  2. introl.com · 2026-02-01T00:00:00
  3. semiengineering.com · 2024-09-17T14:00:45
  4. tomshardware.com · 2026-06-30T11:00:00
  5. fast.ece.illinois.edu
  6. eetimes.com
  7. tomshardware.com
  8. eetimes.com · 2019
  9. trendforce.com · 2026-07-21
  10. en.wikipedia.org
  11. computeexpresslink.org · March 12, 2024
  12. networkworld.com · Aug 18, 2023
  13. rambus.com
  14. synopsys.com
  15. aminext.blog
  16. kad8.com · 2026
  17. penguinsolutions.com
  18. thelec.net · 2026-05-13
  19. finance.biggo.com
  20. mobilityforesights.com
  21. montage-tech.com · 2025-08-27

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

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