CXL memory and memory expanders
BOTTLENECKCXL controller ASIC IP margin is captured by Astera Labs, bottlenecking memory pool deployment despite commoditized DRAM.
Memory pools attached over CXL protocol, expanding beyond CPU socket limits. Enables larger inference KV-cache and model-weight staging for multi-GPU serving. CXL controller ASIC vendors Astera Labs and Montage Technology capture IP margin; DRAM suppliers commoditised.
What the evidence shows
Almost none of the CXL memory modules are buyable on the open market in 2026 in any volume resembling 'stock'.
cosolvic.comRESCORED JUL 2026fragmentedscaling15 companies
Who controls it
MicronSamsungSK Hynix+12 more tracked
$2.0B market · 2025source
Where it sits in the stack
Takes in: DDR5 DRAM dies, CXL controller ASIC, PCIe Gen5 interface
Sends on: Expanded memory pool accessible over CXL fabric from host CPU
Related nodes
Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.
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