Process design kits (PDKs), DFM, and OPC/mask data prep

Why the concentration exists

A process design kit is a set of files used to model a fabrication process for the design tools that create integrated circuits. The PDK is created by the foundry to define a specific technology variation for its processes. It contains design rules, design guides, device symbols, Pcells, netlisting, and techfiles that together enable designers to lay out circuits that the foundry can manufacture.[8][1][13]

PDKs standardize access to process information in the fabless semiconductor model, where designers license the kit under non-disclosure agreements to protect intellectual property. Because they include controlled technology, PDKs are subject to export regulations under the Export Administration Regulations on the Commerce Control List. PDKs classified under ECCN 3E001 or 3E991 require a Technology Control Plan with access restrictions.[3][10]

Design for manufacturing recommended rules and lithographic process checking can be added to the PDK to help designers avoid layouts that might cause catastrophic failure. PDKs can contain hundreds of gigabytes of data, which foundries work to streamline into interactive kits. The fracture process that converts raw design data into a format compatible with mask shop patterning tools can take hours to complete.[5][20][18]

What the evidence shows

Who supplies it

Foundries create PDKs for their own process technologies and provide them to customers. Tower Semiconductor offers PDKs that support most major EDA vendors' design flows through a front-to-back integrated custom design environment. GlobalFoundries provides PDKs that streamline hundreds of gigabytes of process data into usable kits for designers.[8][7][20]

EDA vendors collaborate with foundries to develop and validate PDKs for specific process nodes. Synopsys and Intel Foundry jointly develop PDKs for advanced nodes such as Intel 18A and Intel 14A, integrating construction, timing, extraction, and signoff-grade multiphysics analysis. Silvaco provides PDKs for multiple semiconductor foundries to enable its custom analog design tools.[19][9]

TSMC released the semiconductor industry's first interoperable process design kit for advanced technology in July 2009, developed in collaboration with Synopsys and Ciranova. Mentor Graphics and TSMC jointly released a TSMC-qualified process design kit for the 0.13 micron mixed-mode and RF CM013RG process on November 30, 2006. SpringSoft supported TSMC's 40-nanometer interoperable process design kit in May 2010 as a founding member of the Interoperable PDK Library Alliance.[11][16][17]

What it depends on, and what depends on it

PDKs sit between foundry process technology and fabless design teams, translating manufacturing capabilities into design constraints. The kit provides the EDA components and collateral needed to take customer concepts from idea to high-volume manufacturing. A PDK serves as the building block for the foundry and process technology relationship.[19]

Foundries use PDKs to optimize the design process and enable reuse of intellectual property and other process building blocks. TSMC's Open Innovation Platform includes interoperable EDA interface formats co-developed between TSMC and its design tool partners. The platform encompasses interoperable EDA technology files for multiple process nodes.[4][12][14]

Where it sits in the stack

What would break it

Open-source PDK initiatives aim to reduce foundry lock-in by providing portable process design data. The SkyWater 130nm PDK is an open-source process design kit that includes design rules, DRC, LVS, behavioral models, and standard cells for digital and analog design. This PDK is used with Yosys synthesis on platforms such as ChipVerify and in educational contexts like the Zero to ASIC course.[15][21]

Chinese EDA vendors have achieved progress in device modeling and PDKs but still face gaps compared to international EDA giants. Domestic solutions in China have developed competitive strengths in many point-tool areas, including board-level DFM tools from local vendors. However, a fully integrated end-to-end toolchain remains a work in progress for Chinese vendors.[2]

Export controls create barriers to PDK access for designers in certain countries. PDKs that meet technical parameters described in ECCN 3E001 or 3E991 require controlled access through Technology Control Plans. PDKs that do not meet these parameters are classified as EAR99, which carries fewer restrictions.[10]

What to watch

The OpenPDK standard, developed under the umbrella of Si2, began work last year and has not yet delivered actual PDKs. This second portable PDK standard aims to provide an alternative approach to foundry-specific kits. The initiative's progress toward producing usable process design kits remains pending.[6]

Intel Foundry's PowerVia backside power delivery innovation required new physical design, routing, and verification approaches to be embedded directly into PDK content. PDKs for Intel 18A and Intel 14A are under joint development by Synopsys and Intel Foundry. These kits will integrate construction, timing, extraction, and signoff-grade multiphysics analysis for Intel's advanced nodes.[19]

Related nodes

Sources

1. anysilicon.com · 2026-03-10T23:35:42
2. allpcb.com · 2025-09-17T00:00:00
3. grokipedia.com · 2026-01-14T01:20:41
4. semiengineering.com · 2026-01-30T22:03:50
5. semiengineering.com · 2018-11-08T16:41:14
6. semiwiki.com · 2024-08-22T15:55:24
7. towersemi.com · 2025-01-02T09:08:11
8. en.wikipedia.org · 2025-12-12T02:32:14
9. silvaco.com · 2023-06-16T17:46:10
10. blink.ucsd.edu
11. pr.tsmc.com · 2009/07/21
12. pr.tsmc.com · 2009/05/27
13. tsmc.com · 2019-04-03
14. pr.tsmc.com · 2010/04/07
15. chipverify.com
16. design-reuse.com · 2006-11-30
17. design-reuse.com · May 25, 2010
18. appliedsmartfactory.com
19. synopsys.com · Jun 10, 2026
20. gf.com
21. zerotoasiccourse.com · 2020-11-12