L1CHOKEPOINT
Semiconductor Manufacturing
Turning sand into a working AI chip is among the most difficult industrial processes humans have ever built. It requires photolithography machines that only ASML makes, cleanrooms held to atomic tolerances, and process knowledge that only TSMC and a tiny cluster of equipment and materials firms possess. A single leading-edge fab costs over $20 billion and takes years to build, which means the supply of advanced chips is effectively fixed in the near term by decisions made long ago.
WHY IT'S A CHOKEPOINT
This is the most concentrated cluster of chokepoints on the map. CoWoS packaging, EUV lithography, actinic mask inspection, HBM stacking, ABF substrates and EDA each run through one or two suppliers worldwide. ASML builds every EUV scanner on the planet. TSMC prints almost every leading-edge chip.
Signals
- TSMC is ramping CoWoS to ~125-130k wafers/month by end-2026, up from ~85k in early 2026 and well over the 2023 level; CoWoS-L/S is fully booked (TrendForce).
- ASML closed 2025 with a ~€38.8B backlog; a High-NA EUV tool runs ~€350M (ASML filings).
- TSMC holds ~70% of foundry revenue; 2nm wafers price near ~$30,000, a 10-20% premium to 3nm (TrendForce / Counterpoint).
- Ajinomoto holds >95% of ABF substrate film and pushed ~15% AI-film price increases; substrate lead times reached ~24 weeks (company filings).
The investment angle
CoWoS packaging and ABF substrates are the tightest near-term chokepoints, both monopoly-adjacent with no credible second source at scale before 2027, cementing pricing power for TSMC and Ibiden.
Inside this layer, node by node
The atlas data behind this layer: 103 nodes, including 6 chokepoints and 36 bottlenecks. Every node links back into the network map; market figures carry their source.
Patterning silicon wafers into functional ICs via lithography, deposition, etch, and implant steps. Foundries and IDMs set capacity constraints for all downstream AI hardware. Pricing power skews extreme at leading edge (TSMC sub-5 nm) versus commoditized mature nodes.
Equipment processing, inspecting, and characterizing wafers: lithography, etch, deposition, CMP, implant, thermal, clean, track, and packaging tools. Determines node capability and yield in a ~$100B annual market. ASML holds the EUV monopoly; all major vendors earn substantial recurring service revenue.
Measurement and inspection tools plus software that catch defects and control dimensions during fabrication. Yield learning depends on this feedback loop. KLA dominates optical and e-beam inspection; Lasertec holds sole commercial EUV mask inspection.
Processes that assemble bare die into packaged, interconnected devices. Includes 2.5D/3D integration: CoWoS, SoIC, fan-out, HBM stacking, hybrid bonding, and interposers. TSMC CoWoS monopoly is the bottleneck for AI GPU supply through 2026.
Electronic design automation tools and licensed silicon IP used to design chips for fabrication. PDKs, DRC, and process-specific IP are inseparable from manufacturing processes. Synopsys, Cadence, and Siemens hold ~85% of EDA market.
Patterned glass templates that project circuit images onto silicon wafers during lithography. EUV masks require extreme precision and novel materials, creating bottlenecks distinct from wafer fabrication itself. AGC/Hoya control EUV mask blanks; Lasertec holds sole actinic inspection; IMS/NuFlare split advanced mask writing.
Materials consumed during wafer fabrication and packaging: wafers, resists, gases, chemicals, substrates. AI chip demand tightens specifications for EUV resists, high-NA materials, and advanced packaging substrates. Concentration in EUV pellicles, mask blanks, and select ALD precursors creates chokepoints; oligopoly in wafers and gases sustains pricing.
Components and sub-assemblies inside and beneath process tools: vacuum, RF, gas delivery, thermal, wafer handling, electrostatic chucks, and sensors. A single subsystem failure can halt an entire fab line, so spares demand tracks the installed tool base. The market was roughly $20 billion in 2023 and is expected to double by 2030; VAT, MKS, and Advanced Energy capture concentrated recurring revenue.
Design and construction of the physical fab building, cleanroom, sub-fab, and all utility connections. Facility quality determines tool uptime and contamination control over decades. M+W/Exyte dominates hyperscale EPC; US and EU builds cost 2–4× Taiwan due to labour and permitting.
Services and parts sustaining installed semiconductor equipment after sale: maintenance contracts, refurbishment, and spare parts. Extends tool lifespans, especially at mature nodes. ASML, AMAT, Lam, TEL, and KLA earn multi-billion recurring revenues; independent providers gain share as fabs face cost pressure.
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