EDA software and semiconductor IP

Why the concentration exists

EDA development is tightly connected with the development of technology nodes. Foundries encode transistor models, physical characteristics, and design rules in file formats that EDA tools must read. EDA vendors and IP vendors receive early PDK access for tool validation and IP development. Standard cell libraries, memory compilers, and interface IP must be qualified and available for fabless design houses to use.[1][4]

Cadence, Synopsys, and Siemens invest over 30% of revenues in R&D. Synopsys topped the EDA list in patent power at 382.2 with 140 patents in 2011. Cadence ranked 12th with 137 patents at 273.4. Verification and simulation demand massive compute, which limits capacity and creates queue times.[15][18][2]

There is greater risk aversion in IP adoption compared with EDA tool adoption. Semiconductor IP must integrate into constantly evolving hardware and software ecosystems. Arm's licensing program covers almost the entire design side of the semiconductor industry. Arm partners signed a record 175 new licenses in calendar year 2020. This brought the total to 1,910 licenses and 530 licensees.[7][12]

What the evidence shows

Who supplies it

Synopsys is the largest provider of EDA technology in the industry. Both Synopsys and Cadence offer a full platform for EDA software. Companies could design a chip entirely on either platform. Nearly every large semiconductor company uses both products for specific workflows.[5][3]

Arm is the world's leading semiconductor intellectual property supplier. Arm licenses IP cores and collects royalties of 1-4% of chip revenue. Non-reporting IP companies, dominated by Arm, grew 24.7% to $1.413 billion in Q4 2025. Synopsys IP revenue reached $1.7 billion.[22][6][14][10]

EDA and Semiconductor IP revenue grew 10.3% in Q4 2025 to $5.466 billion. This was up from $4.955 billion in the same period in 2024. CAE, the largest EDA category, rose 9.4% to $2.083 billion in Q4 2025. The EDA hardware-assisted verification category surpassed a billion dollars in revenue. Ansys has a reseller channel business of roughly half a billion dollars a year.[14][15]

What it depends on, and what depends on it

EDA tools are used to design integrated circuits, printed circuit boards, and microprocessors. A fabless company might use Arm IP and Synopsys EDA tools to design a chip. The chip is then manufactured at TSMC and sent to ASE for packaging. EDA software tools represent roughly 9-12% of total semiconductor R&D spending.[19][11][10]

Arm runs more than 53 million EDA jobs per week using AWS Batch. Arm is moving the majority of its EDA workloads to AWS. This move is intended to reduce its global datacenter footprint by at least 45%. Arm has realized a 6x improvement in performance time for EDA workflows on AWS.[21][20]

Where it sits in the stack

What would break it

Open-source EDA tools such as OpenROAD and other DARPA-funded initiatives are emerging. These tools are not yet competitive at advanced nodes. Gdsfactory is an open-source platform with more than 1 million downloads and 50 contributors. It offers more than 10 PDKs, including open-source options like Skywater130 CMOS and GlobalFoundries 180nm MCU.[6][23]

Arm's royalty model creates margin pressure for chip companies. This incentivizes RISC-V alternatives. China struggles in production inputs including EDA and core IP. Siemens EDA has sent cooperation invitations to IP startups in South Korea and the United States. The goal is to attract companies focusing on NPUs, AI accelerators, and high-speed interfaces.[6][13][9]

Nvidia made an offer to acquire Arm from Softbank for $40 billion in stock and cash. As of the page's writing, this would be worth about $54 billion due to Nvidia's share price rise. EDA companies like Synopsys and Cadence have built sizable IP portfolios. These portfolios allow them to sell cores alongside software.[12][11]

What to watch

AI and ML will continue to accelerate early-stage design in 2026. Physics-based simulation will remain essential for final verification. The chiplet ecosystem for high-speed digital applications will shift from early adopters to early majority adoption in 2026. 2026 will see the rise of the 'prompt engineer' who interacts with EDA tools through natural language.[16]

The Chips to Systems Conference, DAC 2026, is coming up in Long Beach, California. An Ansys Saber for Power Electronics Design webinar is scheduled for July 29. An Agile CI/CD in Chip Design webinar is scheduled for August 4. A Compensating for PCB laminate anisotropy in SI calculations webinar is also scheduled for August 4.[8][17]

Related nodes

Sources

1. en.wikipedia.org · 2026-04-26T23:13:36
2. rescale.com · 2026-06-24T20:52:31
3. generativevalue.com · 2025-09-27T15:00:40
4. newsletter.semianalysis.com · 2026-05-22T11:20:53
5. synopsys.com · 2025-09-09T00:00:00
6. jaredwatkins.com · 2026-04-25T00:00:00
7. eetimes.com · 2015-02-17T19:00:00
8. eetimes.com · 2026-07-14T15:51:20
9. eu.36kr.com · 2025-08-04T00:00:00
10. newsletter.semianalysis.com · 2026-05-22T07:26:28
11. umbrex.com · 2025-04-24T17:48:07
12. cset.georgetown.edu · 2020
13. cset.georgetown.edu
14. semiengineering.com · Q4 2025
15. semiengineering.com
16. semiengineering.com · 2026-01-29
17. semiengineering.com
18. eetimes.com · 01.10.2013
19. arm.com
20. newsroom.arm.com · December 17, 2020
21. aws.amazon.com · February 2022
22. os.mbed.com
23. github.com