EDA software and semiconductor IP
BOTTLENECKSynopsys anchors an EDA oligopoly whose process design kits and rule checks are inseparable from each fab's manufacturing, blocking qualified alternatives.
Electronic design automation tools and licensed silicon IP used to design chips for fabrication. PDKs, DRC, and process-specific IP are inseparable from manufacturing processes. Synopsys, Cadence, and Siemens hold ~85% of EDA market.
Electronic design automation tools and licensed silicon intellectual property used to design chips that will be fabricated in L5.1 fabs; included in L5 because PDKs, DRC, and process-specific IP are inseparable from manufacturing; core chip architecture is L4.
What the evidence shows
Synopsys, Cadence, and Siemens EDA collectively control approximately 75% of the global EDA market as of 2024.
matrixbcg.comStandard cell libraries, memory compilers, and interface IP require several months of engineering lead time to qualify for fabless design houses.
newsletter.semianalysis.comSynopsys tools are embedded deeply in the design flows of TSMC, Samsung Foundry, Intel Foundry, and leading fabless semiconductor companies.
intellectualmarketinsights.comWho controls it
Where it sits in the stack
Takes in: Design intent, process design kit (PDK), device models
Sends on: Verified layout/GDSII, photomask data for L5.1
Related nodes
Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.
GET THE BRIEFING