Pure-play leading-edge logic foundries (sub-5 nm)
BOTTLENECKTSMC alone runs sub-5 nm logic at scale, locking AI-chip customers into multi-year supply deals with no qualified second source until at least the late 2020s.
Contract fabs manufacturing at 3 nm, 2 nm, and below with gate-all-around transistor architectures. Sole commercial source for the most advanced AI processors through approximately 2027. TSMC holds near-monopoly pricing power and locks customers into long-term supply agreements.
Why the concentration exists
Pure-play leading-edge logic foundries manufacture chips at nodes below 5 nanometers for customers without their own fabrication facilities. These foundries operate at the frontier of transistor scaling, where gate-all-around nanosheet architectures at 2nm and below deliver lower power consumption and reduced gate leakage compared to earlier FinFET designs. The shift to nanosheets allows more transistors to be packed into a given area for improved performance. Leading-edge nodes provide the highest profit margins for foundries, and demand currently exceeds supply by a wide margin.[2][10][11]
The capital requirements to enter this market create an insurmountable barrier for most potential competitors. A single 2nm fab line costs $15-20 billion and requires 3-5 years of construction. The total number of entities capable of financing a leading-edge fab has contracted to three: TSMC, Samsung, and Intel. GlobalFoundries and UMC halted their respective 7nm efforts in 2018, effectively ceding the leading-edge to those three players. Every sub-7nm logic chip produced anywhere in the world passes through an ASML EUV scanner, with High-NA EUV scanners costing approximately $350 million each.[6][7][3][5]
The technology progression demands sustained R&D investment over many years. TSMC shipped the world's first 7nm FinFET process in 2018, followed later by Samsung. TSMC became the first foundry to move 5nm FinFET technology into volume production in 2020, and the first to move 3nm FinFET into high-volume production in 2022. This first-mover advantage compounds over successive nodes, as each generation builds on the learning and yield improvements from the previous one.[3][8][9]
What the evidence shows
TSMC holds ~90%-plus share of sub-5nm logic where the entire AI profit pool sits.
investmentcase.substack.comDemand for leading-edge nodes currently exceeds supply by a wide margin.
semiengineering.comSamsung offers 3nm GAA with a roadmap to 2nm and high-volume EUV capacity, evaluated as a strategic second source.
latterly.orgWho controls it
No independently verified market-size figure is published for this node yet.
What it depends on, and what depends on it
Apple stands as the largest customer for leading-edge capacity, representing 25% of TSMC's revenue in 2023. Apple and Intel were reported to be testing their proprietary chip designs with TSMC's 3nm production as of July 2021. Between late 2025 and early 2026, AI compute chips started moving from 4nm to 3nm even as high-end smartphone and PC processors had not yet migrated to 2nm at scale. This sequencing reflects the premium that AI accelerator customers place on performance advantages at the most advanced nodes.[14][12][17]
The foundries depend on a concentrated upstream supply chain for critical inputs. ASML is the only producer of EUV scanners at commercial scale globally, with its Veldhoven, Netherlands facility serving as the sole source of leading-edge EUV exposure capability. Intel was first to receive High-NA EUV systems, followed by TSMC and Samsung Foundry. TSMC's Fab 18 in Tainan, Taiwan has capacity of more than 1 million wafers per month for 5nm and 3nm process nodes using EUV lithography.[5][15]
Where it sits in the stack
Takes in: Fabless/IDM chip design, PDKs, photomasks, EUV-exposed wafers
Sends on: Leading-edge logic wafer with complete transistor stack; wafer-sorted known-good die
19 upstream · 4 downstream
What would break it
Yield challenges at Samsung constrain its ability to serve as a meaningful second source. Samsung Foundry's 3nm GAA yields improved to approximately 60-70% by 2026, but still trail TSMC's N3 yields of 80% or higher. This yield gap translates directly into higher effective costs for customers choosing Samsung over TSMC. Intel Foundry's entry into the market offers a potential third source, but its foundry business remains early in building the customer relationships and manufacturing track record that TSMC has established over decades.[18][4]
Capacity bottlenecks at the most advanced nodes may persist for years. AI demand has created capacity constraints at 3nm and 2nm nodes and across advanced packaging since 2023, with analysts not expecting meaningful relief until 2027 at the earliest. TSMC's N3 node family is operating at essentially 100% utilization, with N3 wafer pricing estimated at $20,000-22,000 per 300mm wafer for baseline N3E in 2026. This tight supply allows TSMC to charge scarcity premiums and lock customers into long-term supply agreements.[17][18]
What to watch
TSMC's 2nm platform technology (N2) started volume production in 4Q25 as planned, featuring gate-all-around nanosheet transistors. N2P, a 5% speed-enhanced version of N2 with full GDS compatibility, targets mass production in 2026. The N2 node promises a 15% performance gain and a 30% reduction in power consumption compared to the 3nm process, with greater than 1.15x chip density increase from the previous node. These improvements will drive the next generation of AI accelerators and high-performance computing chips.[8][10][11][16]
Advanced packaging capacity remains a critical constraint alongside leading-edge wafer supply. TSMC's CoWoS capacity is projected to reach 70,000 to 80,000 wafers per month by late 2025, and potentially 120,000 to 130,000 wafers per month by the end of 2026. This packaging technology enables the multi-chip designs that dominate AI accelerator architectures. The foundry sector grew 30% year-over-year in Q1 2026, primarily driven by surging AI GPU and ASIC orders including for advanced packaging.[16][1]
Geographic diversification efforts are underway but face technical and policy constraints. TSMC's Fab 21 in Phoenix, Arizona began limited production of 4nm chips in late 2024 and is ramping toward 3nm and eventually 2nm. TSMC has announced a second fab in Japan with production scheduled to begin in 2027, though Taiwan's evolving restrictions on the transfer of advanced chipmaking technologies overseas might interfere with plans to produce 2nm chips in Japan. Intel 14A remains on track for risk production in Q4 2026.[13][19][18]
Related nodes
Sources
- counterpointresearch.com · 2026-06-05T00:00:00
- semiengineering.com · 2026-04-30T15:16:55
- semiengineering.com · 2018
- tomshardware.com · 2025
- semiconductorx.com
- semiconductorx.com
- semiconductorx.com
- tsmc.com
- tsmc.com · 2020
- research.tsmc.com · 2024
- research.tsmc.com · 2024
- en.wikipedia.org · July 2021
- siliconcanals.com · 2025
- britannica.com · 2024
- blackridgeresearch.com
- markets.financialcontent.com · Q2 and Q3 2025
- sourceability.com · May 12, 2026
- supplyics.com · 2026
- eastasiaforum.org · 16 January 2026
Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.
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