Leading-edge memory fabs - DRAM and HBM
BOTTLENECKThree firms produce HBM with complex TSV stacking, and their limited wafer capacity directly constrains AI accelerator shipments.
Fabs producing DRAM and high-bandwidth memory (HBM) with through-silicon via stacking for AI accelerators. HBM supply constrains GPU and AI chip output; capacity is ~23% of total DRAM wafers by 2026. Samsung, SK Hynix, and Micron capture 5-8x pricing premium over commodity DRAM.
Fabs producing commodity DRAM and high-bandwidth memory (HBM) on leading nodes (1-beta/1-gamma DRAM); HBM base-die and buffer-die fabrication includes through-silicon via (TSV) processing.
Why the concentration exists
HBM combines vertically stacked DRAM chips with ultra-wide data paths, creating the optimal balance of bandwidth, density, and energy consumption for AI workloads. HBM is much more expensive to produce than DDR5 and carries a warranted price premium. HBM4 doubles bandwidth through adoption of 2,048 I/O terminals and improves power efficiency by more than 40% compared to the previous generation. SK Hynix implemented over 10Gbps operating speed in HBM4, exceeding the JEDEC standard of 8Gbps. HBM4 sticks with microbumps, postponing hybrid bonding.[1][19][18]
Leading-edge memory fabs require multi-billion-dollar capital investments that have steadily increased over the past few decades. These heavy capital investments mean that suppliers must operate with high utilization rates to generate cash profits and earn a payback. SK Hynix committed 103 trillion won (nearly US $77 billion) in chip investment from 2024 through 2028 alone. The capital intensity creates a structural barrier to new entrants in the HBM market. Only three companies currently manufacture HBM memory modules because of the scale of investment required.[2][23][13]
What the evidence shows
Building leading-edge DRAM fabs requires multi-year construction and lengthy ramp-up before volume production.
newsletter.semianalysis.comHigh-end HBM supply is constrained by process, packaging, and yield factors, making rapid ramp-up difficult.
finance.biggo.comWho supplies it
South Korea commands a majority share of DRAM fabrication capacity, well ahead of its nearest rivals. SK Hynix operates four semiconductor memory production facilities in South Korea: three fabs at its headquarters in Icheon (M10, M14, and M16) and one fab in Cheongju (M15). Samsung's Pyeongtaek P1 and P2 are DRAM and NAND memory fabs in South Korea. Micron operates DRAM fabs in Boise, USA and Hiroshima, Japan, and a NAND/DRAM fab in Singapore. SK Hynix's dominance stems from its early leadership in stacked DRAM design and its strong specialized South Korea talent base.[20][17][5]
Who controls it
What it depends on, and what depends on it
All leading AI accelerators deployed for GenAI training and inference use HBM. Each AI GPU can integrate 6 to 12 HBM stacks. An NVIDIA H100 SXM5 paired with six HBM3 stacks achieves approximately 3.35 TB/s of memory bandwidth, roughly 65 times the bandwidth of a dual-channel DDR5 desktop system. HBM stacks represent approximately 34% to 45% of total AI accelerator manufacturing cost across current-generation platforms. HBM demand remains strong because AI workloads require this combination of bandwidth and capacity.[1][24][12][22]
HBM3E modules deliver 9.2 Gbps per pin, 1 TB/s bandwidth per stack, and capacity up to 24GB per stack. Samsung's 12-layer HBM3E modules offer up to 1,280 GB/s bandwidth and 36 GB capacity. Micron's 12-Hi HBM4 samples offer 2.8 TB/s bandwidth and 11 Gbps pin speeds. HBM4 is targeting 1.5 to 2.0 TB/s bandwidth per stack, 16-high stacks with 64GB+ capacity. HBM3E modules process at 4.8 terabytes per second.[24][21][12][13]
TSMC's most important role in the AI chip era is leveraging its advanced packaging technologies, such as CoWoS, to help integrate AI processors with external high-performance memory such as HBM. SK Hynix's HBM4 is built using TSMC's 12nm logic process. Samsung uses a thin non-conductive film with thermocompression bonding in its 12-layer HBM3E. SK Hynix's HBM4 doubles bandwidth through adoption of 2,048 I/O terminals and improves power efficiency by more than 40% compared to the previous generation. SK Hynix implemented over 10Gbps operating speed in HBM4, exceeding the JEDEC standard of 8Gbps.[7][21][13][19]
Where it sits in the stack
Takes in: Silicon wafer, specialty etch and deposition gases, TSV process chemicals
Sends on: DRAM die (commodity) or HBM base-die/buffer-die (via TSV process)
What would break it
SK Hynix and others announce ambitious capacity doublings over the coming years, yet new fabs take time, often two to four years from groundbreaking to full production. SK Hynix plans to scale 1c-node monthly wafer capacity from approximately 20K to 160K to 190K 300mm wafers by end-2026, an approximately 8x to 9x increase from a single-node base. SK Hynix chairman Chey Tae-won said the company will double its memory wafer capacity within five years. Samsung is targeting approximately 50% HBM production capacity growth in 2026, but qualification timelines for HBM4 remain the binding constraint.[6][22][11]
Software paradigms such as near-memory computing and ANSI HBM-aware APIs may arise as the memory wall shifts. Academia continues exploring 3D DRAM, of which HBM is one example, and alternatives. UCIe offers nearly 12x better performance than HBM3E, with energy per bit going down by an order of magnitude from 2pJ to 0.25pJ. Eliyan's proprietary Nulink standard claims even greater improvements. The industry also explores software techniques that make flash storage mimic DRAM behavior for certain workloads, potentially easing pressure on traditional memory.[3][4][6]
What to watch
SK Hynix is investing 19 trillion won (about $13 billion) in a new facility called P&T7 in Cheongju, South Korea, due to be completed by the end of 2027. SK Hynix's M15X fab in Cheongju had equipment installation starting in early 2026. SK Hynix brought forward the launch of the first cleanroom at its Yongin fab from May 2027 to February 2027. SK Hynix committed an additional KRW 21.6 trillion (approximately USD 15 billion) for its first semiconductor fabrication plant by the end of December 2030, bringing cumulative investment in its first Yongin fab to KRW 31 trillion. SK Hynix plans to complete the Yongin Semiconductor Cluster by 2027, which will include four state-of-the-art fabs.[9][10][20]
Samsung's P3 fab is expected to reach 115,000 wafers per month by end-2026. Samsung's P4 will start second-phase mass production by Q2 2026 at 60,000 wafers. Construction on Samsung's new P5 fab is set to resume in October 2025 with production planned for late 2027. Micron is advancing new fab construction in Clay, New York, and Boise, Idaho. Micron reports that its full year HBM4 capacity is already sold out under binding contracts.[15][10][16]
SK Hynix will invest $3.87 billion in a new advanced memory packaging facility in Indiana, expected to start operations in the second half of 2028, focusing on HBM4 and HBM4E memory products. SK Hynix's advanced packaging lines are at capacity through 2026. SK Hynix completed development and prepared world-first mass production of HBM4 as of September 12, 2025. HBM4 volume is targeted for 2026 and beyond. For Project Stargate, Samsung and SK Hynix together committed to up to 900,000 DRAM wafer starts per month, representing roughly 35-40% of global DRAM wafer capacity.[8][14][19][12]
Related nodes
Sources
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