Plasma etch - dielectric etch

Why the concentration exists

Dielectric etch forms the insulating structures that protect conducting parts in semiconductor devices. The process uses fluorine-based chemistries to remove oxide layers, creating oxide isolators that separate devices. It also etches via holes and trenches for metal conductive paths in interconnect schemes. These insulating features are essential for preventing electrical shorts between adjacent conductors.[1][18]

A plasma etcher generates plasma from process gas using a high-frequency electric field, typically at 13.56 MHz. The process gas is typically oxygen or a fluorine-bearing compound. Higher power levels generate higher plasma densities, which lead to faster etching rates. However, excessive power causes high-energy ion bombardment that can damage the silicon wafer and reduce selectivity.[9][3]

Deep etching for 3D NAND requires sustaining 30 to 50 kilowatts of power without arcing. The process etches approximately 100nm holes through multilayer oxide-nitride stacks with 200 or more layers. These holes reach depths up to 10 micrometers with extremely tight profile requirements. For nanosheet transistors, channel release steps require extremely high selectivity to remove silicon-germanium without modifying silicon.[6]

What the evidence shows

Who supplies it

Lam Research is the recognized market leader in plasma etch equipment. The company's plasma etch business is built on decades of innovation in reactive ion etch and atomic layer etching technologies. Lam introduced dielectric atomic layer etching capability on its Flex dielectric etch systems in September 2016. This was the first use of plasma-enhanced atomic layer etching in production for dielectric films.[10][8]

Key companies in the plasma etch dielectric etch market include Lam Research, Applied Materials, Hitachi High-tech, and Tokyo Electron. Other suppliers include Oxford Instruments, NAURA Technology Group, SPTS Technologies, AMEC, Ulvac, Samco, and Plasma Therm. Applied Materials offers the Dielectric Etch Super e Centura system with up to 50 percent improvement in throughput over previous systems. Mattson Technology has more than 600 paradigm E plasma etch chambers installed globally.[14][15][12]

What it depends on, and what depends on it

Dielectric etch systems operate with gases including SF6, CHF3, argon, and oxygen. Mass-flow controllers ensure accurate delivery of these process gases to the chamber. The chamber reaches base pressure in the range of 3x10^-5 Torr. Working pressure ranges from 10 milliTorr to 800 milliTorr for different etching applications.[4]

The process creates through-silicon vias that allow packaging of chips together. It also forms structures for micro-electromechanical systems. In back-end-of-line interconnect flows, dielectric etch creates trenches in the interlayer dielectric. A bilayer liner is then deposited onto the etched feature to obtain a copper diffusion barrier and adhesion.[1][2]

Tokyo Electron developed dielectric etch technology for memory channel holes in 3D NAND flash with over 400 layers. This process enables 10-micrometer-deep etching in 33 minutes. The new process reduces global warming potential by 84 percent compared with previous technologies. Tokyo Electron presented this research at the 2023 Symposium on VLSI Technology and Circuits in Kyoto.[13]

Where it sits in the stack

What would break it

Tokyo Electron introduced its Acrevia gas cluster beam system in July 2024. The system enables precise sidewall modification and reduces line-edge roughness. It also corrects pattern defects post-EUV lithography. Applied Materials expanded its patterning solutions portfolio in February 2024 by introducing the Sym3 Y Magnum etch system for 2nm and below.[16]

Lam Research introduced Lam Cryo 3.0 cryogenic etch technology on July 31, 2024. The technology etches memory channels with depths up to 10 microns and less than 0.1 percent profile deviation. It offers a 40 percent reduction in energy consumption per wafer compared to conventional etch processes. The process also delivers up to 90 percent reduction in emissions.[7][16]

Atomic layer etching tools are vital for multi-layer pattern transfer as feature sizes shrink below 10nm. Conventional etching tools saturate at these dimensions. The dielectric atomic layer etching process delivers twice the selectivity improvement over previous dielectric etch technologies. This atomic-level control enables scaling logic devices to 10nm and below.[17][5][8]

What to watch

Lam Research's Sense.i platform, launched in March 2020, enables process performance for logic and memory device roadmaps. The platform addresses dielectric etch applications among other critical processes. Continued development of such platforms will support advancing device nodes. The industry requires etch solutions that can handle increasing layer counts in 3D NAND and finer features in logic devices.[11]

Related nodes

Sources

1. lamresearch.com · 2024-06-20T18:12:15
2. pubs.aip.org · 2024-06-07T00:00:00
3. wevolver.com · 2023-12-14T15:17:45
4. matter-systems.gatech.edu
5. electronicdesign.com · September 2016
6. semiengineering.com
7. investor.lamresearch.com · July 31, 2024
8. newsroom.lamresearch.com · 2016-09-06
9. en.wikipedia.org
10. klover.ai
11. knowledge-sourcing.com · March 2020
12. mattson.com
13. tel.com · 2023.06.09
14. archivemarketresearch.com
15. semiconductoronline.com
16. knowledge-sourcing.com · July 2024
17. impedans.com
18. sst.semiconductor-digest.com