Leading-edge memory fabs - 3D NAND flash

200-plus-layer 3D NAND with hybrid-bonded CMOS requires extreme technical mastery and massive scale that only incumbents can afford, blocking new entrants.

Fabs producing 3D NAND flash with 200-plus vertical layers and hybrid-bonded CMOS architecture. Storage for AI training datasets and edge inference devices. YMTC challenges incumbent cost structures; layer-count leadership and scale economics drive average selling prices for Samsung, SK Hynix, Kioxia, and Micron.

Fabs producing flash memory using vertical stacking of 200-plus cell layers; increasingly adopting CMOS-bonded-array (CBA) architecture via wafer-to-wafer hybrid bonding.

What the evidence shows

Samsung Electronics held over 11.6% market share in 2025.

Western Digital holds a 15% global market share in NAND.

en.unibetter-ic.com

YMTC is on track to surpass SK hynix and Micron in shipment volumes as early as this year.

koreaherald.com

RESCORED JUL 2026oligopolyscaling

Who controls it

Western DigitalSamsung ElectronicsSK hynix

$24B market · 202517.56% CAGRsource

Where it sits in the stack

Takes in: Silicon wafer, high-aspect-ratio etch gases (NF3, WF6), deposition precursors

Sends on: 3D NAND flash die

depends onEtch equipment Sputtering targets Plasma etch - dielectric etch

feeds intoConventional packaging - flip-chip BGA/FCBGA/LGA Conventional packaging - wire-bond (QFN, QFP, BGA)

Related nodes

Pure-play leading-edge logic foundries (sub-5 nm)Leading-edge memory fabs - DRAM and HBM Established/mid-range logic foundries (7-28 nm)Mature/trailing-edge logic foundries (40 nm - 350 nm)Specialty process foundries Integrated device manufacturers (IDMs)

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

GET THE BRIEFING