Interposers (silicon, organic/bridge, glass)

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TSMC controls most advanced silicon interposer capacity and rival foundries lack the needed packaging expertise to qualify as second sources.

Intermediate routing layers between chiplets and organic package substrate; includes passive silicon, organic/bridge, and emerging glass interposers. Enables high-density interconnect for chiplet-based AI accelerators. Value distributed across foundry, OSAT, and substrate suppliers.

Why the concentration exists

Silicon interposers provide high I/O density through established semiconductor manufacturing processes, but add $30 to $100 to chip cost depending on size. They are made using back-end processes that limit them to high-performance applications where density requirements justify the expense. The manufacturing competes directly with chip production for wafer slots, which creates structural supply constraints at foundries.[4][23][24]

Organic interposers offer a cost-effective alternative using well-established supply chains and traditional subtractive manufacturing like wet etching. They work well for applications where routing requirements exceed 10 micrometers and operating frequencies stay below approximately 5 GHz. Their flexibility creates mechanical limitations and lower I/O density compared to silicon alternatives.[2][23]

Glass interposers can be produced in large panel formats measuring 730 by 900 millimeters or even 2400 by 2800 millimeters, compared to silicon interposer wafers at 150 to 300 millimeters. This panel format enables greater manufacturing throughput and potentially lower cost per unit. However, glass faces manufacturing challenges including surface defects, lower thermal conductivity than silicon, and susceptibility to cracking during processing.[5][23][24]

What the evidence shows

Ajinomoto, Unimicron, Ibiden have high supply concentration in organic ABF substrates.

semiconductorx.com

Every silicon interposer wafer slot competes with chip production, creating a structural bottleneck at TSMC.

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Threat of new entrants is low due to high technical and capital barriers.

hdinresearch.com

RESCORED JUL 2026oligopolyscaling5 companies

Who supplies it

TSMC operates the dominant silicon interposer platform through its CoWoS-S technology, which has been in production since 2012 and supports interposer sizes up to 3.3 times reticle size. The company's CoWoS-R using RDL interposers has been in volume production since 2023, while CoWoS-L at 3.5 times reticle size entered volume production in 2024. TSMC announced a capacity expansion for its CoWoS technology to meet rising demand from AI accelerator customers.[9][21]

Intel has mass-produced its EMIB bridge technology since 2017 and its Foveros-S 2.5D packaging since 2019. EMIB allows the use of low-cost organic materials for the overall substrate while providing high-density interconnect where needed. Most OSATs and substrate suppliers have since developed their own versions of EMIB technology.[3][11]

GlobalFoundries offers 65PKG silicon interposers manufactured at its Malta, New York facility with production qualification at TRL9 and no restrictions on foundry origin of mounted die. ISI, a Molex company, produces over 100 new interposer designs annually at its ITAR-compliant facility in Camarillo, California. Samsung offers silicon interposer solutions through its Silicon Strip Based Package platform.[12][16][17][19]

Who controls it

TSMCIntel+3 more tracked

No independently verified market-size figure is published for this node yet.

What it depends on, and what depends on it

NVIDIA's H100 GPU uses a silicon interposer to connect its processor to 80 GB of HBM3 memory, delivering 3.35 terabytes per second of bandwidth. AMD's Instinct MI300X employs a silicon interposer with 192 GB of HBM3 memory delivering 5.3 terabytes per second of bandwidth. These AI accelerators depend on interposer density to achieve the bandwidth required for large language model training.[18]

TSMC's CoWoS-S platform can fit up to eight HBM3 stacks on a single interposer measuring 858 square millimeters, supporting 6.6 terabytes per second of bandwidth while keeping power below 400 watts. Google's next-generation TPU, codenamed HumuFish, uses a silicon interposer nearly 80 square centimeters or nine times reticle size. These large interposer designs push against the size limits of current manufacturing technology.[15][18]

Organic interposers serve applications where cost sensitivity outweighs extreme performance requirements, including wearables, IoT sensors, and mid-range smartphones. The technology simplifies supply chains and testing while reducing total cost of ownership and shortening lead times. Glass interposers target designs where organic limits are most constraining and silicon interposer cost and size ceilings create pressure.[1][2]

Where it sits in the stack

Takes in: Chiplets, silicon/organic/glass routing substrate, TSV metallisation

Sends on: Integrated multi-chip interposer assembly

depends onWafer fabrication - foundries and IDMs Bonding wire Semiconductor capital equipment Semiconductor materials and consumables Industrial metals

feeds into2.5D packaging - silicon interposer (CoWoS-S and variants)2.5D packaging - organic/bridge interposer (CoWoS-L, EMIB)

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What would break it

Glass interposers offer superior flatness and thermal stability critical for ultra-fine circuitry in future 2nm and 1.6nm AI processors. The first commercial applications of glass-based advanced packaging are expected by late 2027. Panel economics could create an opening for glass where organic limits constrain and silicon interposer cost and size ceilings pinch.[1][20][22]

TSMC is exploring 12-inch monocrystalline silicon carbide for thermal substrates in advanced 3D IC packaging, with semi-insulating SiC potentially used as part of the silicon interposer layer. SiC thermal conductivity reaches 400 to 500 watts per meter-kelvin compared to ceramic substrates offering 200 to 230 watts per meter-kelvin. This material substitution could address thermal management challenges in high-power AI accelerators.[8][14]

What to watch

TSMC will initiate volume production of 5.5 times reticle size interposers in 2026 after completing certification in 2025. The company expects to produce 14-reticle-sized interposers capable of carrying 20 3D-stacked compute chiplets and 20 HBM5 modules in 2028. By 2029, TSMC expects interposers over 14 reticle sizes supporting up to 24 HBM5E stacks.[6][10]

Rapidus began pilot production of its 600-millimeter-by-600-millimeter glass interposer in June 2025 at a cleanroom facility in Chitose, Hokkaido. The company will showcase the glass interposer prototype starting December 17, 2025, at SEMICON Japan 2025. This panel format yields more than ten times as many interposers as traditional 300mm silicon wafers.[7]

TSMC plans to introduce CoPoS large-size glass interposer technology around 2029, with small-scale trial production as early as 2028. Monthly capacity could reach approximately 12,000 wafers per month in 2029. Early CoPoS panel specifications are around 310 by 310mm, with subsequent versions scalable to 515 by 510mm and 750 by 620mm.[13]

Sources

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

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