2.5D packaging - organic/bridge interposer (CoWoS-L, EMIB)

BOTTLENECK

Supply is constrained by embedded bridge die shortages and organic substrate capacity, and a qualified second source is years away.

2.5D integration using organic or embedded silicon-bridge interposer instead of full silicon interposer. Lower cost than CoWoS-S for applicable AI GPU designs; adopted for next-gen products from 2025. Constrained by embedded bridge die supply and organic substrate capacity.

Why the concentration exists

Organic and bridge-interposer 2.5D packaging route fine-pitch signals between a logic die and multiple HBM stacks without relying on a full silicon interposer. CoWoS-L replaces the large silicon interposer of CoWoS-S with an organic redistribution layer (RDL) interposer into which small local silicon interconnect (LSI) bridges are embedded, which is why it scales past the area limit of monolithic silicon interposers. EMIB goes further by dropping the large interposer entirely, embedding a silicon bridge die inside a cavity cut into a standard build-up organic substrate and routing die-to-die traffic across it at 5-micron line/space pitch in the first generation.[6][8][12][15]

What the evidence shows

Production of the carrier and the CoWoS assembly runs captive at TSMC — there is no merchant market.

semiconductorx.com

RESCORED JUL 2026oligopolyscaling4 companies

Who supplies it

Two foundries dominate silicon-bridge 2.5D packaging for AI accelerators, each running its own variant. Intel supplies EMIB from captive capacity, embedding the bridge into ABF-based FCBGA substrates it builds with a small group of qualified partners, including Ibiden, Unimicron, and AT&S. Intel's first commercial EMIB part was the Stratix 10 FPGA in 2016, and Ponte Vecchio later combined EMIB with Foveros to integrate 47 active chiplets.[3][7][11][12]

TSMC supplies CoWoS-L from its own fabs and brought the first-generation 3.5× reticle variant into volume production in 2024. CoWoS-L is the variant used in Nvidia's Blackwell B100 and B200 GPUs, which connect two compute chiplets through LSI bridges and an RDL interposer at 10 TB/s chip-to-chip bandwidth. Outside the two foundries, ASE has demonstrated FOCoS-B, a fan-out RDL structure that embeds eight silicon bridge dies alongside two ASICs and eight HBM2e modules, with FO modules measuring 47 × 31 mm in a 78 × 70 mm package body and 0.8 µm die-to-die connections.[5][9][10][13][14][17][18]

Substrate-level supply is more concentrated than die-level supply. Ajinomoto Fine-Techno holds approximately 95% of the global market for ABF film, the critical insulating film used in every high-performance AI chip substrate, making organic-substrate 2.5D packaging dependent on a single upstream film supplier even when multiple substrate fabricators are qualified.[19]

Who controls it

TSMCIntelSamsung+1 more tracked

No independently verified market-size figure is published for this node yet.

What it depends on, and what depends on it

Organic and bridge-interposer 2.5D packaging is the assembly layer between leading-edge AI compute dies and stacks of high-bandwidth memory. It uses an organic RDL interposer or a patterned FCBGA organic substrate as the mechanical carrier, with one or more small silicon bridges embedded into the carrier to carry the dense die-to-die signals that organic layers alone cannot handle. The finished package then mounts on a system PCB through a conventional ball grid array.[6][8][10][12]

What it makes possible is system-level integration at reticle-plus sizes. CoWoS-L pairs two large compute chiplets with up to 12 HBM3E stacks in Nvidia's Blackwell B100/GB200, totaling 208 billion transistors in one package. Intel's EMIB family scales in the opposite direction from monolithic silicon interposers because the bridges sit locally, so each additional bridge extends package area without reticle-limited silicon area.[11][13][14][15]

Where it sits in the stack

Takes in: Chiplets, embedded bridge die, organic substrate with cavity

Sends on: 2.5D multi-chip module with organic/bridge interposer

depends onPure-play leading-edge logic foundries (sub-5 nm)Bonding wire Interposers (silicon, organic/bridge, glass)Wafer fabrication - foundries and IDMs Semiconductor capital equipment Semiconductor materials and consumables Industrial metals

view in atlas

What would break it

Cost remains the clearest point of fragility for the interposer-based alternative. Bernstein analysts estimate EMIB packaging in the low hundreds of dollars per chip, against an estimated $900 to $1,000 for CoWoS on a Rubin-class accelerator, and Intel claims roughly 90% wafer utilization for bridge dies compared with about 60% utilization for large interposers. Those two figures together explain why some customer designs originally scoped for CoWoS were ported to Foveros with no modification, a shift Intel has confirmed.[1][4]

What to watch

Three reticle-size milestones define the next capacity wave. TSMC is planning larger CoWoS interposer sizes of up to 9.5× reticle by 2027, CoWoS-L is expected to reach about 9× reticle by 2027 starting from a 3.5× reticle base, and EMIB-M is expected to support 8× to 12× reticle sizes from 2026 to 2027. These generations are not arriving fast enough for current AI accelerator demand, so each one carries near-term allocation significance.[1][2]

A specific patent and standard tracks round out the watch list. US patent 11955431B2, assigned to Intel, covers interposer structures and methods for 2.5D and 3D packaging and has a priority date of 2018-05-15 with publication on 2024-04-09. The CHIPS Alliance's AIB standard now covers 6G data rates for bridge packaging and is targeted primarily at the mil-aero ecosystem, which sets a near-term ceiling on merchant adoption of the bridge die-to-die interface standard.[16][20]

Sources

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

GET THE BRIEFING