HBM stacking - TSV and mass reflow/thermocompression bonding

Why the concentration exists

High-Bandwidth Memory stacks DRAM dies vertically using through-silicon vias (TSVs), which are copper-filled vertical interconnects with diameters of approximately 5-6 micrometers and pitches of 40-55 micrometers. Each die contains 1,024 to 2,048 TSVs depending on the generation, and dies are thinned to approximately 50 micrometers before stacking. A defective TSV in any layer can fail the entire stack, which means TSV yield loss scales directly with stack height.[8][20][21]

Two bonding approaches dominate current HBM production. SK Hynix uses Mass Reflow Molded Underfill (MR-MUF), which reflows and underfills all layers in a single step using liquid protective material injected between layers. Samsung and Micron use Thermal Compression with Non-Conductive Film (TC-NCF), which presses and bonds one layer at a time with insulating film placed between DRAM chips that melts under heat to form connections.[3][6][15][21]

Bonding equipment must achieve single-digit or sub-micron alignment accuracy for TSV pitches around 40 micrometers, with even pressure distribution critical to avoid warpage that compounds over many layers. Thermal resistance rises sharply beyond 12-layer stacks because the three-dimensional structure traps heat and amplifies thermomechanical stress. JEDEC specifications limit total stack height to 720 micrometers for HBM3 and earlier generations, expanded to 775 micrometers for newer standards to accommodate 16-layer configurations.[1][2][6][11][12]

What the evidence shows

Who supplies it

Hanmi Semiconductor holds a 90% share of the global HBM TC bonder market for HBM3E mass production, having launched the world's first TSV Dual Stacking TC Bonder for HBM in 2017. The company secured 71.2% global market share by revenue in the HBM TC bonder market through the third quarter of 2025, with cumulative revenue of $247.7 million. Hanmi has filed 130 patents related to HBM equipment since 2002, covering TSV stacking and thermocompression bonding.[22][24]

Taiwanese OSAT providers have developed thermal compression bonding techniques specifically optimized for HBM stacks, supported by government subsidies for advanced packaging R&D. The concentration of TSV technology leaders and HBM packaging specialists in Hsinchu Science Park creates knowledge spillover effects that facilitate yield optimization and prototype-to-production scaling.[5]

What it depends on, and what depends on it

HBM stacks sit on a silicon interposer alongside the GPU or AI accelerator die, bonded together using TSMC's CoWoS (Chip on Wafer on Substrate) advanced packaging process. This integration into CoWoS interposer packages represents a second bottleneck after HBM production itself. A single HBM3E stack delivers approximately 1.2 TB/s of bandwidth compared to approximately 38 GB/s for a DDR5 DIMM.[15][17]

HBM4 is expected to offer more than 1.4 times the bandwidth and 1.3 times the capacity per memory chip compared to HBM3/HBM3E, while burning only 70 percent of the power. SK Hynix exhibited the world's first 16-layer HBM4 sample at CES 2026, with single-stack capacity increased to 48GB. Samsung's 12-layer HBM3E achieves bandwidth of up to 1,280 GB/s and capacity of 36 GB while maintaining the same height as 8-layer stacks.[6][11][18]

SK Hynix developed HBM with TSV structure for the first time in the world in 2013 and mass-produced it, creating the MR-MUF technology that improves thermal dissipation by more than 10 degrees Celsius compared to competitors. High volume manufacturing of HBM began at a Hynix facility in Icheon, South Korea, in 2015, with Samsung Electronics beginning early mass production of HBM2 in January 2016.[9][10]

Where it sits in the stack

What would break it

SK Hynix's exclusive contract with Namics for underfill material used in MR-MUF is approaching expiration, which could reshape HBM supply chain dynamics. SK Hynix may stick with MR-MUF for HBM4 16-high, extending the sole-source dependency on Namics underfill. Diversifying the supplier base is common practice for leading fabs, which could threaten Hanmi's dominant position.[4][23]

What to watch

SK Hynix verified a 12-die HBM stack bonded through hybrid bonding as of April 28, 2026, and ordered a hybrid bonding inline system jointly developed by Applied Materials and Besi for approximately KRW 20 billion. The industry expects hybrid bonding adoption starting with HBM4, with gradual introduction likely from the second half of 2026 or into 2027 as 16-high products are commercialized.[7][14]

Samsung will begin shipping HBM4 chips to Nvidia in February 2026, while Micron has stated that its full 2026 HBM4 production capacity is sold out. SK Hynix has delivered HBM4 samples to Nvidia but has not disclosed when its HBM4 chips will ship to GPU makers. Samsung plans to introduce hybrid bonding technology as early as HBM4E and is providing 16-layer HBM samples based on hybrid bonding for evaluation.[16][19]

SK Hynix plans to start mass-producing 16-layer HBM4 memory in 2026 and will introduce hybrid bonding technology starting from the HBM4E generation, which will use 20-layer stacked DRAM chips. SK Hynix expects to launch HBM5 around 2029 to 2030 using hybrid bonding, which will enter full-scale mass production from that point.[13][19]

Related nodes

Sources

1. newsletter.semianalysis.com · 2025-10-03T20:56:42
2. mdpi.com · 2025-07-02T00:00:00
3. photoncap.net · 2026-05-04T07:58:48
4. techinvestments.io · 2026-03-16T11:34:19
5. semiconductorinsight.com · 2026-02-16T06:10:58
6. semiengineering.com
7. trendforce.com · 2026-04-29
8. semiconductorx.com
9. news.skhynix.com · 2013
10. en.wikipedia.org · 2015
11. eu.36kr.com · 2026-01-16
12. viksnewsletter.com
13. en.sedaily.com · 2029-2030
14. wccftech.com · 2026-04-28
15. techtimes.com
16. blocksandfiles.com · Wed 28 Jan 2026
17. luna3.ai
18. nextplatform.com
19. eu.36kr.com · July 22
20. enostech.com
21. zonglen.com
22. asiae.co.kr · 22 Dec.2025
23. forcedalpha.com · January 2026
24. mk.co.kr · 2017