2.5D packaging - silicon interposer (CoWoS-S and variants)

BOTTLENECK

TSMC ships the standard CoWoS-S interposers for AI GPUs and its order backlog is the binding constraint on accelerator supply.

Multiple chiplets on a passive silicon interposer with fine-pitch redistribution, then organic substrate. TSMC CoWoS-S is the standard for AI GPUs and HPC. Order backlog makes it the binding constraint on AI accelerator supply.

Why the concentration exists

CoWoS-S is a 2.5D packaging technology in which multiple active silicon dies sit side by side on a passive silicon interposer, which is then mounted on an organic substrate. The interposer is fabricated using a process resembling front-end wafer manufacturing, but contains no transistors and consists only of metal routing layers. Through-silicon vias are formed using Deep Reactive Ion Etch, followed by insulation and barrier deposition via CVD, copper seed deposition via PVD, and copper filling via electrochemical deposition. After known-good logic and HBM dies are flip-chip attached, the interposer is thinned to around 100 micrometers to reveal the TSVs before dicing and attachment to a build-up package substrate with C4 solder bumps.[1][8][9]

Deep trench capacitors embedded in the interposer provide high capacitance density that fulfils the instantaneous current demand of high-speed computing applications. An ultra-thin 50-micrometer silicon interposer with TSV technology has been developed to achieve ultra-small form factor package solutions. A representative test chip with thousands of micro-bumps at 45-micrometer pitch has been fabricated for a 28-nanometer logic die mounted on a large silicon interposer with copper TSVs. These features enable the high bandwidth and power delivery required by AI accelerators.[5][14]

What the evidence shows

TSMC runs captive CoWoS production with no merchant market for interposers or assembled modules.

semiconductorx.com

TSMC's CoWoS capacity is the single binding global constraint on the AI accelerator market.

semiconductorx.com

Lead times for CoWoS at TSMC are 52 to 78 weeks with bookings extending into 2027.

techtimes.com

RESCORED JUL 2026near-monopolyscaling3 companies

Who supplies it

TSMC held a 60% share of the 2.5D and 3D stacking market in 2024, leveraging its CoWoS and SoIC technologies. The platform has supplied more than 100 products to more than 20 customers since CoWoS-S entered mass production in 2012. More than 60 product tape-outs are currently in production or development on the CoWoS platform. This concentration reflects TSMC's early entry into 2.5D packaging and the qualification barriers that protect its position.[21][18][2]

TSMC's CoWoS capacity is fully booked by tier-1 customer Nvidia, with Nvidia securing more than 70% of TSMC CoWoS-L capacity for 2025. Alchip, a Taiwanese design firm, acts as a middleman for over 30 customers using TSMC's CoWoS platform but can only secure about 50% of its requested capacity because of Nvidia's dominance. TSMC is also a key provider of 2.5D silicon interposers to Google and Amazon for their custom AI silicon. The result is that second-tier customers face chronic allocation shortfalls.[6][3][4]

Who controls it

TSMC+2 more tracked

$1.3B market · 202533.3% CAGRsource

What it depends on, and what depends on it

CoWoS packaging is used in NVIDIA H100 and H200 GPUs, in AMD MI300 which integrates CPU, GPU, and HBM on a single interposer, and in Intel Ponte Vecchio which uses EMIB to connect more than 40 chiplets. NVIDIA A100 and H100 use the CoWoS-S variant, while NVIDIA Blackwell B200 and AMD MI300X use CoWoS-L. The AMD MI355X combines eight 3-nanometer GPU chiplets with 6-nanometer IO dies and 288 gigabytes of HBM3E memory in eight 12-Hi stacks. Every major AI accelerator family therefore depends on access to CoWoS or a competing 2.5D flow.[19][22][25]

The completed CoWoS module stacks a logic die and two or more HBM stacks on the silicon interposer, which sits on an organic FCBGA laminate substrate that connects to the board. NVIDIA's Blackwell B100 and B200 were the first processors to use CoWoS-L in production, achieving 10 terabytes per second of chip-to-chip bandwidth and packing 208 billion transistors into one package. Broadcom's 3.5D XDSiP enables 6,000 square millimeter packages with 12 HBM stacks. The interposer thus serves as the high-density interconnect plane that makes chiplet integration viable.[1][17][20]

The silicon interposer often accounts for 50% to 70% of the packaging cost, and in some cases the packaging is more expensive than the chip itself. Micro-bumps on the interposer provide high-density traces delivering up to 50 terabits of bandwidth using 10,000 wires each running at 5 gigabits per second. Silicon interposers allow signals to travel only two or three millimeters but offer much finer wires and higher bump density than organic packages, which can run signals 25 times further but at 5 to 10 times lower density. These trade-offs explain why the interposer is both expensive and indispensable.[23][11]

Where it sits in the stack

Takes in: GPU/HPC chiplets, HBM stacks, silicon interposer, ABF organic substrate

Sends on: 2.5D multi-chip module (H100, H200, B100/B200 class AI GPUs)

depends onPure-play leading-edge logic foundries (sub-5 nm)HBM stacking - TSV and mass reflow/thermocompression bonding Bonding wire Interposers (silicon, organic/bridge, glass)Wafer fabrication - foundries and IDMs Semiconductor capital equipment Semiconductor materials and consumables Industrial metals IC packaging substrates Advanced packaging materials

feeds intoSemiconductor test - ATE, burn-in, and probe

view in atlas

What would break it

CoWoS-L replaces the full silicon interposer with an organic redistribution-layer substrate and embedded local silicon interconnect bridges, enabling effective interposer areas above 3,000 square millimeters. IDTechEx predicts that 2.5D silicon bridge solutions will soon replace silicon interposers as the primary choice for packaging HPC chips. Intel's EMIB-T, introduced in 2025, uses small embedded silicon bridges rather than a full interposer, trading raw bandwidth density for lower cost. The shift toward bridges reduces the silicon interposer's role as the binding constraint.[16][10][17]

What to watch

TSMC's CoWoS capacity is effectively sold out through 2027, with the foundry targeting 47,000 wafers per month by 2026, up from 23,000 wafers per month. Broadcom's 3.5D XDSiP is scheduled to enter production in early 2026 with 6,000 square millimeter packages and 12 HBM stacks. Intel's EMIB-T is scaling from 2026, supporting large packages up to 120 by 180 millimeters with bump pitches below 45 micrometers. These milestones will determine whether alternative 2.5D flows can absorb demand that TSMC cannot serve.[7][20][17][24]

TSMC has announced high-volume production of its first-generation CoWoS-L at 3.5 times reticle size. CoWoS-S has evolved to support silicon interposers up to 3 times reticle size through stitching, with TSMC developing a 3 times maximum reticle size CoWoS-S interposer that supports two large SoCs and 8 HBM3 stacks. The second-generation CoWoS uses an ultralarge silicon interposer up to 1,200 square millimeters made by a two-mask stitching process. Larger interposer sizes extend the addressable compute and memory that can be integrated in a single package.[26][6][18][15]

SK Hynix's West Lafayette, Indiana facility is targeting the second half of 2028 for the start of 2.5D packaging operations, with a planned investment of $3.87 billion partially funded by $458 million in CHIPS Act grants and loans. The site will package HBM chips with silicon interposers and integrate them with partner dies into thermally optimized 2.5D modules, and will be the first US facility to offer high-volume 2.5D packaging for third-party AI customers. TSMC fabricates CoWoS interposers at back-end facilities in both Taiwan and Arizona, providing a partial geographic diversification of the captive supply base. The timeline for non-Taiwan capacity to reach meaningful volume remains the key uncertainty for supply chain planners.[12][7][13]

Sources

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

GET THE BRIEFING