2.5D packaging - silicon interposer (CoWoS-S and variants)
BOTTLENECKTSMC ships the standard CoWoS-S interposers for AI GPUs and its order backlog is the binding constraint on accelerator supply.
Multiple chiplets on a passive silicon interposer with fine-pitch redistribution, then organic substrate. TSMC CoWoS-S is the standard for AI GPUs and HPC. Order backlog makes it the binding constraint on AI accelerator supply.
What the evidence shows
TSMC runs captive CoWoS production with no merchant market for interposers or assembled modules.
semiconductorx.comTSMC's CoWoS capacity is the single binding global constraint on the AI accelerator market.
semiconductorx.comLead times for CoWoS at TSMC are 52 to 78 weeks with bookings extending into 2027.
techtimes.comWho controls it
Where it sits in the stack
Takes in: GPU/HPC chiplets, HBM stacks, silicon interposer, ABF organic substrate
Sends on: 2.5D multi-chip module (H100, H200, B100/B200 class AI GPUs)
Related nodes
Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.
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