3D-IC - SoIC/wafer-on-wafer/die-on-wafer hybrid bonding

TSMC SoIC is the primary platform for logic-on-logic AI chiplets, and qualifying a second source requires years of joint process development with customers.

Vertical logic die stacking with direct copper-to-copper hybrid bonding at sub-10-micron pitch. Enables monolithic-equivalent scaling for AI accelerators when planar scaling slows. TSMC SoIC is the primary platform for logic-on-logic AI chiplets.

What the evidence shows

Hybrid bonding equipment is supplied by a concentrated set of vendors: BESI, EV Group, AMAT, TEL, ASMPT, SET, Shibaura, and SUSS Microtec.

newsletter.semianalysis.com

Hybrid bonding remains primarily limited to 3D stacking of dies; TSMC's SoIC and Intel's Foveros Direct are cited examples.

tspasemiconductor.substack.com

AMD's 3D V-Cache stacks SRAM on top of CPU core die using TSMC's SoIC platform.

RESCORED JUL 2026oligopolyscaling5 companies

Who controls it

TSMCIntel+3 more tracked

No independently verified market-size figure is published for this node yet.

Where it sits in the stack

Takes in: Known-good die/wafer pairs, ultra-flat CMP-prepared bonding surfaces, bonding activation chemistry

Sends on: 3D-stacked die with fine-pitch direct copper interconnect

depends onPure-play leading-edge logic foundries (sub-5 nm)Deposition equipment Assembly and packaging equipment (back-end tools)Wafer fabrication - foundries and IDMs Semiconductor capital equipment Semiconductor materials and consumables Industrial metals Thermo-compression and hybrid-bonding tools

Related nodes

2.5D packaging - silicon interposer (CoWoS-S and variants)2.5D packaging - organic/bridge interposer (CoWoS-L, EMIB)Fan-out wafer-level and panel-level packaging (FOWLP/FOPLP)HBM stacking - TSV and mass reflow/thermocompression bonding Silicon photonics co-packaged optics (CPO)Conventional packaging - flip-chip BGA/FCBGA/LGA

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

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