3D-IC - SoIC/wafer-on-wafer/die-on-wafer hybrid bonding

Why the concentration exists

Hybrid bonding creates permanent, direct copper-to-copper bonds between stacked semiconductor components without solder bumps. The technology achieves ultra-fine-pitch interconnects typically below 10 micrometres, enabling pitches as small as single micrometres and bandwidth exceeding 1000 GB/s. TSMC's SoIC technology enables sub-10μm bonding pitches with 0.25X the bump-pad pitch over existing schemes. This eliminates the need for micro-bumps and achieves sub-micron density that traditional 3D ICs cannot match.[2][8][15][17]

Wafer-on-wafer hybrid bonding offers through-silicon vias at one-tenth the pitch of chip-on-wafer hybrid bonding. Wafer-on-wafer achieves TSVs at approximately 1.7-micron pitch while chip-on-wafer operates at 17-micron pitch, enabling 10,000 TSVs in the area where chip-on-wafer offers only 100. Imec has demonstrated wafer-on-wafer hybrid bonding with a 400-nanometer pitch and chip-on-wafer hybrid bonding with a 2-micrometer pitch. Face-to-face stacking enables 14,000 signals per square millimetre compared to 1,500 signals per square millimetre with face-to-back stacking using TSVs.[5][7][9][14]

The process requires extreme precision in wafer thinning and surface preparation to achieve fine-pitch copper-to-copper bonds. A new wafer thinning process enables finer pitch at 1 micrometre with improved silicon thickness uniformity. Serious wafer edge offset issues have been encountered during process development, requiring root cause analysis and process improvement. EV Group achieved 100-percent void-free bonding yield of multiple die from a complete 3D system-on-a-chip in a single transfer process using its GEMINI FB automated hybrid bonding system in July 2022.[3][4][16]

What the evidence shows

Who supplies it

Hybrid bonding equipment is supplied by a concentrated set of vendors including BESI, EV Group, Applied Materials, Tokyo Electron, ASMPT, SET, Shibaura, and SUSS Microtec. Additional equipment suppliers include Kulicke and Soffa Industries, TORAY ENGINEERING, KLA Corporation, Lam Research Corporation, DISCO Corporation, Beijing U-Precision Tech, Hanmi Semiconductor, and Onto Innovation. Applied Materials is co-developing die-based hybrid bonding equipment with Besi. The equipment market concentration reflects the specialised technical requirements for void-free bonding at sub-micron pitches.[1][17][18]

The patent landscape for hybrid bonding includes over 1,600 related patent families with more than 280 key inventions identified as of September 2024. Leading patent assignees include TSMC, Adeia, YMTC, Intel, and Samsung. YMTC holds 25 key patent families related to hybrid bonding addressing 3D memory architectures and heterogeneous integration. Adeia Semiconductor holds multiple patents for low temperature hybrid bonding including structures using nanoparticles. AMD holds patents for bond pads for low temperature hybrid bonding.[19][20][21][22]

What it depends on, and what depends on it

Hybrid bonding technology emerged in 2005 with Ziptronix's direct bond interconnect technology. Tessera, now Adeia, acquired Ziptronix in 2015. Sony first used copper hybrid bonding for CMOS image sensors in 2016, licensing the technology from Ziptronix which is now part of Xperi. This established the commercial viability of hybrid bonding in high-volume manufacturing before its adoption for logic-on-logic stacking in AI accelerators.[8][21]

AMD's 3D V-Cache stacks SRAM on top of CPU core die using TSMC's SoIC platform and was the first adopter of die-on-wafer hybrid bonding in 2022. Graphcore's Bow IPU was announced as the world's first 3D wafer-on-wafer hybrid bonded processor on March 3, 2022, making Graphcore the vanguard customer for TSMC's wafer-on-wafer SoIC technology. Broadcom and Fujitsu are using TSMC's face-to-face SoIC technology with 9 micrometre pitches for Fujitsu's Monaka supercomputer CPU.[3][6][7][9]

HBM4 will be the first HBM generation to adopt hybrid bonding at the die-to-die interface, ramping through 2026. TSMC's SoIC hybrid bonding supports a 12-high HBM stack with a total thickness of approximately 600 micrometres. The industry is working on hybrid bonding to enable new 3D DRAM types including three-die stacked DRAMs. YMTC's key patents propose new 3D memory device designs involving vertically stacked NAND, DRAM, and SRAM arrays integrated through hybrid bonding.[10][11][12][22]

Where it sits in the stack

What would break it

Xperi has developed a new version of its hybrid bonding technology and is licensing it to others. Adeia has licensed hybrid bonding patents to Qorvo. Intel and TSMC are exploring copper-to-copper hybrid bonding for fine-pitch 2.5D and 3D-ICs. The licensing model for hybrid bonding intellectual property could enable broader adoption beyond the current concentrated supplier base if equipment vendors and foundries successfully implement licensed processes.[10][18][21]

What to watch

Fujitsu's Monaka supercomputer CPU using TSMC's face-to-face SoIC technology with 9 micrometre pitches is expected to volume produce in 2027. HBM4 will ramp through 2026 as the first HBM generation to adopt hybrid bonding at the die-to-die interface. Imec and EV Group demonstrated wafer-to-wafer hybrid bonding with 200-nanometre interconnect pitch and record high overlay accuracy in a 2026 press release.[9][11][14]

TSMC's 2-nanometer chips are poised for mass production and will transition from FinFET to Gate-All-Around or NanoSheet. At sub-1nm scale, components will be stacked vertically as CFET according to imec. Hybrid bonding enables backside power delivery by interconnecting wafers and copper bumps directly, as highlighted by TSMC Senior Vice President Dr. Kevin Zhang at the 2024 Technology Symposium. Nvidia's Blackwell GPU generates 100W of heat per square centimetre, and future chips may generate five times that, requiring liquid cooling as air cooling's ceiling is 100W per square centimetre.[13]

Related nodes

Sources

1. newsletter.semianalysis.com · 2025-10-29T21:22:05
2. idtechex.com · 2024-04-18T00:00:00
3. darpa.mil
4. ieeexplore.ieee.org
5. spectrum.ieee.org · 2029
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7. newsletter.semianalysis.com · 2022-03-03
8. semiengineering.com · 2021
9. tomshardware.com · 2025
10. semiengineering.com
11. semiconductorx.com
12. 3dincites.com
13. english.cw.com.tw · 2025-01-15
14. imec-int.com · 2024
15. 3dincites.com · Oct 29, 2018
16. evgroup.com · 2022-07-12
17. insightaceanalytic.com · 2026-03-05
18. skyquestt.com · 2024
19. knowmade.com · end of 2023
20. patents.google.com
21. knowmade.com · 2024
22. chiplet-marketplace.com · January 2024