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10 layers580 nodes2,376 dependencies9 chokepoints112 bottlenecks6,500+ companiesnode size = companies identified

Semiconductor test - ATE, burn-in, and probe

BOTTLENECK

Two vendors dominate ATE supply and longer test times for AI chips create throughput bottlenecks.

Automated test equipment and test operations for functional and parametric testing of packaged or bare die. Longer test times for HBM and AI ASICs create throughput bottlenecks at advanced nodes. Teradyne and Advantest hold ~85%+ ATE market share.

Automated test equipment and test operations for functional and parametric testing of packaged or bare die; covers SoC/logic ATE, memory ATE, wafer probe/sort, burn-in, and wafer-level burn-in.

What the evidence shows

Advantest, Teradyne, and Cohu collectively hold about 55% of the ATE market.

mordorintelligence.com

Advantest virtually monopolizes ATE supply for AI and advanced-node chips.

tspasemiconductor.substack.com

Handlers and probers are largely dominated by Japanese firms TEL and Tokyo Seimitsu.

tspasemiconductor.substack.com
RESCORED JUL 2026oligopolyscaling10 companies

Who controls it

AdvantestTeradyne+8 more tracked
$15B market · 20256.12% CAGRsource

Where it sits in the stack

Takes in: Packaged or probed die, test program, loadboard/DIB

Sends on: Tested, binned die with known-good designation

view in atlas

Related nodes

2.5D packaging - silicon interposer (CoWoS-S and variants)2.5D packaging - organic/bridge interposer (CoWoS-L, EMIB)Fan-out wafer-level and panel-level packaging (FOWLP/FOPLP)3D-IC - SoIC/wafer-on-wafer/die-on-wafer hybrid bondingHBM stacking - TSV and mass reflow/thermocompression bondingSilicon photonics co-packaged optics (CPO)

Full scorecard, owner shares, supply edges and the full tracked roster are in the desk letter.

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